Status register.
| CMDCRCFAIL | Command response received (CRC check failed). |
| DATACRCFAIL | Data block sent/received (CRC check failed). |
| CMDTIMEOUT | Command response timeout. |
| DATATIMEOUT | Data timeout. |
| TXUNDERRUN | Transmit FIFO underrun error. |
| RXOVERRUN | Receive FIFO overrun error. |
| CMDRESPEND | Command response received (CRC check passed). |
| CMDSENT | Command sent (no response required). |
| DATAEND | Data end (data counter is zero). |
| STARTBITERR | Start bit not detected on all data signals in wide bus mode. |
| DATABLOCKEND | Data block sent/received (CRC check passed). |
| CMDACTIVE | Command transfer in progress. |
| TXACTIVE | Data transmit in progress. |
| RXACTIVE | Data receive in progress. |
| TXFIFOHALFEMPTY | Transmit FIFO half empty. |
| RXFIFOHALFFULL | Receive FIFO half full. |
| TXFIFOFULL | Transmit FIFO full. |
| RXFIFOFULL | Receive FIFO full. |
| TXFIFOEMPTY | Transmit FIFO empty. |
| RXFIFOEMPTY | Receive FIFO empty. |
| TXDATAAVLBL | Data available in transmit FIFO. |
| RXDATAAVLBL | Data available in receive FIFO. |
| RESERVED | Reserved. The value read from a reserved bit is not defined. |